Sciweavers

118 search results - page 22 / 24
» A technique for minimizing power during FPGA placement
Sort
View
ICCAD
2001
IEEE
127views Hardware» more  ICCAD 2001»
14 years 4 months ago
What is the Limit of Energy Saving by Dynamic Voltage Scaling?
Dynamic voltage scaling (DVS) is a technique that varies the supply voltage and clock frequency based on the computation load to provide desired performance with the minimal amoun...
Gang Qu
GLVLSI
2007
IEEE
134views VLSI» more  GLVLSI 2007»
14 years 1 months ago
Sleep transistor distribution in row-based MTCMOS designs
- The Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. This technology utilizes high-Vth sleep transistors to reduce subthreshol...
Chanseok Hwang, Peng Rong, Massoud Pedram
SIGGRAPH
1998
ACM
13 years 11 months ago
Interactive Multi-Resolution Modeling on Arbitrary Meshes
During the last years the concept of multi-resolution modeling has gained special attention in many fields of computer graphics and geometric modeling. In this paper we generaliz...
Leif Kobbelt, Swen Campagna, Jens Vorsatz, Hans-Pe...
CASES
2007
ACM
13 years 11 months ago
Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking
We propose a technique which leverages configurable data caches to address the problem of cache interference in multitasking embedded systems. Data caches are often necessary to p...
Rakesh Reddy, Peter Petrov
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
14 years 1 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...