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DATE
2005
IEEE
113views Hardware» more  DATE 2005»
14 years 2 months ago
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda...
MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
14 years 2 months ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...
KI
2002
Springer
13 years 8 months ago
Spatial Strategies in Human-Robot Communication
This paper deals with various kinds of mental representations available for linguistic instruction in spatial humanrobot interaction. After a survey of the literature on spatial r...
Thora Tenbrink, Kerstin Fischer, Reinhard Moratz
DAC
2008
ACM
14 years 10 months ago
Multiprocessor performance estimation using hybrid simulation
With the growing number of programmable processing elements in today's MultiProcessor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware...
Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer L...
BMCBI
2005
140views more  BMCBI 2005»
13 years 9 months ago
Dissecting systems-wide data using mixture models: application to identify affected cellular processes
Background: Functional analysis of data from genome-scale experiments, such as microarrays, requires an extensive selection of differentially expressed genes. Under many condition...
J. Peter Svensson, Renée X. de Menezes, Ing...