Sciweavers

48 search results - page 4 / 10
» AHIR: A Hardware Intermediate Representation for Hardware Ge...
Sort
View
AUSDM
2008
Springer
238views Data Mining» more  AUSDM 2008»
13 years 9 months ago
Graphics Hardware based Efficient and Scalable Fuzzy C-Means Clustering
The exceptional growth of graphics hardware in programmability and data processing speed in the past few years has fuelled extensive research in using it for general purpose compu...
S. A. Arul Shalom, Manoranjan Dash, Minh Tue
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 11 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
CASES
2007
ACM
13 years 11 months ago
Compiler generation from structural architecture descriptions
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
Florian Brandner, Dietmar Ebner, Andreas Krall
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 10 months ago
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
Randal E. Bryant
CAV
2011
Springer
365views Hardware» more  CAV 2011»
12 years 10 months ago
BAP: A Binary Analysis Platform
Abstract. BAP is a publicly available infrastructure for performing program verification and analysis tasks on binary (i.e., executable) code. In this paper, we describe BAP as we...
David Brumley, Ivan Jager, Thanassis Avgerinos, Ed...