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VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
14 years 4 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
EDBT
2010
ACM
188views Database» more  EDBT 2010»
14 years 2 months ago
DEDUCE: at the intersection of MapReduce and stream processing
MapReduce and stream processing are two emerging, but different, paradigms for analyzing, processing and making sense of large volumes of modern day data. While MapReduce offers t...
Vibhore Kumar, Henrique Andrade, Bugra Gedik, Kun-...
ATC
2008
Springer
14 years 27 days ago
Scheduling for Reliable Execution in Autonomic Systems
Abstract. Scheduling the execution of multiple concurrent tasks on shared resources such as CPUs and network links is essential to ensuring the reliable operation of many autonomic...
Terry Tidwell, Robert Glaubius, Christopher D. Gil...
ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
14 years 21 days ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson