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» Accurate and scalable reliability analysis of logic circuits
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DAC
2010
ACM
13 years 11 months ago
LUT-based FPGA technology mapping for reliability
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
Jason Cong, Kirill Minkovich
ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
14 years 19 days ago
Technology Mapping for Reliability Enhancement in Logic Synthesis
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
Zhaojun Wo, Israel Koren
ISPD
2006
ACM
103views Hardware» more  ISPD 2006»
14 years 1 months ago
High accurate pattern based precondition method for extremely large power/ground grid analysis
In this paper, we propose more accurate power/ground network circuit model, which consider both via and ground bounce effects to improve the performance estimation accuracy of on-...
Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hon...
DAC
2010
ACM
13 years 11 months ago
Towards scalable system-level reliability analysis
State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems: (1) ...
Michael Glaß, Martin Lukasiewycz, Christian ...
COMCOM
2006
101views more  COMCOM 2006»
13 years 7 months ago
A combined group/tree approach for scalable many-to-many reliable multicast
Abstract--In this paper we present the design, implementation, and performance analysis of Group-Aided Multicast (GAM), a scalable many-tomany reliable multicast transport protocol...
Wonyong Yoon, Dongman Lee, Hee Yong Youn, Seung-Ik...