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» Accurate power estimation for large sequential circuits
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ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 4 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 2 months ago
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints
Sleep transistor insertion is one of today’s most promising and widely adopted solutions for controlling stand-by leakage power in nanometer circuits. Although single-cycle powe...
Andrea Calimera, Luca Benini, Enrico Macii
DATE
2007
IEEE
89views Hardware» more  DATE 2007»
14 years 2 months ago
Computing synchronizer failure probabilities
— System-on-Chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchro...
Suwen Yang, Mark R. Greenstreet
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
14 years 1 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
DAC
1997
ACM
14 years 5 days ago
Sequence Compaction for Probabilistic Analysis of Finite-State Machines
- The objective of this paper is to provide an effective technique for accurate modeling of the external input sequences that affect the behavior of Finite State Machines (FSMs). T...
Diana Marculescu, Radu Marculescu, Massoud Pedram