433 search results - page 14 / 87 » Activity-driven clock design for low power circuits |
166
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CODES
2007
IEEE
16 years 3 days ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
194
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ISQED
2010
IEEE
16 years 19 days ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
180
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DAC
2007
ACM
16 years 6 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
146
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ISCAS
2007
IEEE
16 years 1 days ago
2007
IEEE
— Domino circuits are used to achieve higher system performance than static CMOS techniques. This work briefly surveys domino keeper designs for high fan-in domino circuits. A ne...
