144 search results - page 7 / 29 » Adapting cache line size to application behavior |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
ICS
2005
Tsinghua U.
14 years 2 months ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
RSP
2003
IEEE
14 years 1 months ago
2003
IEEE
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
DATE
2004
IEEE
14 years 7 days ago
2004
IEEE
In this paper, we propose an approach to estimate the Worst Case Response Time (WCRT) of tasks in a preemptive multi-tasking single-processor real-time system with a set associati...
VTS
2011
IEEE
13 years 6 days ago
2011
IEEE
This paper proposes an adaptive multi-bit error correcting code for phase change memories that provides a manifold increase in the lifetime of phase change memories thereby making...