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CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
OOPSLA
2005
Springer
14 years 1 months ago
Using dependency models to manage complex software architecture
An approach to managing the architecture of large software systems is presented. Dependencies are extracted from the code by a conventional static analysis, and shown in a tabular...
Neeraj Sangal, Ev Jordan, Vineet Sinha, Daniel Jac...
ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
13 years 11 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
SIGMETRICS
2008
ACM
116views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
Optimal sampling in state space models with applications to network monitoring
Advances in networking technology have enabled network engineers to use sampled data from routers to estimate network flow volumes and track them over time. However, low sampling ...
Harsh Singhal, George Michailidis
GECCO
2009
Springer
109views Optimization» more  GECCO 2009»
14 years 5 days ago
A genetic algorithm for learning significant phrase patterns in radiology reports
Radiologists disagree with each other over the characteristics and features of what constitutes a normal mammogram and the terminology to use in the associated radiology report. R...
Robert M. Patton, Thomas E. Potok, Barbara G. Beck...