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CODES
2005
IEEE
14 years 4 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
SIGGRAPH
1997
ACM
14 years 2 months ago
A framework for realistic image synthesis
Our goal is to develop physically based lighting models and perceptually based rendering procedures for computer graphics that will produce synthetic images that are visually and ...
Donald P. Greenberg, Kenneth E. Torrance, Peter Sh...
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
14 years 1 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
CVPR
2010
IEEE
14 years 6 months ago
Linear View Synthesis Using a Dimensionality Gap Light Field Prior
Acquiring and representing the 4D space of rays in the world (the light field) is important for many computer vision and graphics applications. Yet, light field acquisition is c...
Anat Levin, Fredo Durand
DAC
2004
ACM
14 years 11 months ago
Architecture-level synthesis for automatic interconnect pipelining
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
Jason Cong, Yiping Fan, Zhiru Zhang