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ASPDAC
2010
ACM
120views Hardware» more  ASPDAC 2010»
13 years 6 months ago
Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method
In this paper, we propose a new wideband model order reduction method for interconnect circuits by using a novel adaptive sampling and error estimation scheme. We try to address t...
Hai Wang, Sheldon X.-D. Tan, Gengsheng Chen
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
13 years 8 days ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
BMCBI
2007
138views more  BMCBI 2007»
13 years 8 months ago
Fast computation of distance estimators
Background: Some distance methods are among the most commonly used methods for reconstructing phylogenetic trees from sequence data. The input to a distance method is a distance m...
Isaac Elias, Jens Lagergren
DATE
2005
IEEE
153views Hardware» more  DATE 2005»
14 years 2 months ago
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices
Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on ...
Smita Krishnaswamy, George F. Viamontes, Igor L. M...
ICCAD
2004
IEEE
147views Hardware» more  ICCAD 2004»
14 years 5 months ago
Interval-valued reduced order statistical interconnect modeling
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
James D. Ma, Rob A. Rutenbar