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144
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GLVLSI
2010
IEEE
310views VLSI» more  GLVLSI 2010»
15 years 7 months ago
Graphene tunneling FET and its applications in low-power circuit design
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Moh...
107
Voted
DAC
2006
ACM
16 years 3 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...
117
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SLIP
2005
ACM
15 years 8 months ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young
155
Voted
ICPPW
2009
IEEE
15 years 9 months ago
SenSORCER: A Framework for Managing Sensor-Federated Networks
—Despite many technology advances, the limited computing power of sensors encumber them from taking part in service-oriented architectures. In recent years, the sensornetworking ...
Sujit Bhosale, Michael W. Sobolewski
124
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AGENTS
1997
Springer
15 years 6 months ago
High-Level Planning and Low-Level Execution: Towards a Complete Robotic Agent
We have been developing Rogue, an architecture that integrates high-level planning with a low-level executing robotic agent. Rogue is designed as the oce gofer task planner for X...
Karen Zita Haigh, Manuela M. Veloso