1322 search results - page 217 / 265 » An Architecture for Distributed Simulation Games |
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
Hardware transactional memory should support unbounded transactions: transactions of arbitrary size and duration. We describe a hardware implementation of unbounded transactional ...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one o...
MOBICOM
2005
ACM
14 years 1 months ago
2005
ACM
People often seek information by asking other people even when they have access to vast reservoirs of information such as the Internet and libraries. This is because people are gr...
ICS
2004
Tsinghua U.
14 years 1 months ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
System-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing complexity...