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» An Architecture for Exploring Large Design Spaces
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ICCD
2007
IEEE
146views Hardware» more  ICCD 2007»
14 years 4 months ago
Exploring DRAM cache architectures for CMP server platforms
As dual-core and quad-core processors arrive in the marketplace, the momentum behind CMP architectures continues to grow strong. As more and more cores/threads are placed on-die, ...
Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Donald New...
CASES
2007
ACM
13 years 11 months ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
WETICE
1999
IEEE
13 years 12 months ago
A Hierarchical Proxy Architecture for Internet-Scale Event Services
The rapid growth of the Web has made it possible to build collaborative applications on an unprecedented scale. However, the request-reply interaction model of HTTP limits the rang...
Haobo Yu, Deborah Estrin, Ramesh Govindan
VLSID
2006
IEEE
112views VLSI» more  VLSID 2006»
14 years 1 months ago
Handling Constraints in Multi-Objective GA for Embedded System Design
Design space exploration is central to embedded system design. Typically this is a multi-objective search problem, where performance, power, area etc. are the different optimizati...
Biman Chakraborty, Ting Chen, Tulika Mitra, Abhik ...
ISCA
2012
IEEE
224views Hardware» more  ISCA 2012»
11 years 10 months ago
A first-order mechanistic model for architectural vulnerability factor
Soft error reliability has become a first-order design criterion for modern microprocessors. Architectural Vulnerability Factor (AVF) modeling is often used to capture the probab...
Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy...