39 search results - page 5 / 8 » An Effective Bump Mapping Hardware Architecture Using Polar ... |
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
MICRO
2000
IEEE
13 years 11 months ago
2000
IEEE
Functionality and performance of EPIC architectural features depend on extensive compiler support. Predication, one of these features, promises to reduce control flow overhead and...
DATE
2010
IEEE
14 years 13 days ago
2010
IEEE
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
ISCA
2002
IEEE
13 years 7 months ago
2002
IEEE
In this paper, we consider the tree task graphs which arise from many important programming paradigms such as divide and conquer, branch and bound etc., and the linear task-graphs...
CODES
2005
IEEE
14 years 29 days ago
2005
IEEE
In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP...