113 search results - page 5 / 23 » An Efficient Two-Level Partitioning Algorithm for VLSI Circu... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discreteand continuous-time domains. Asynchronous propagation ...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Popular repre...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...