76 search results - page 6 / 16 » An Estimation Methodology for Designing Instruction Cache Me... |
RTSS
2009
IEEE
14 years 2 months ago
2009
IEEE
—Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multipro...
RTAS
2008
IEEE
14 years 1 months ago
2008
IEEE
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
This paper presents a methodology for cycle-accurate simulation of energy dissipation in embedded systems. The ARM Ltd. 1 instruction-level cycle-accurate simulator is extended wi...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...