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ISLPED
1995
ACM
122views Hardware» more  ISLPED 1995»
13 years 10 months ago
A multiple clocking scheme for low power RTL design
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...
Christos A. Papachristou, Mark Spining, Mehrdad No...
VTS
2005
IEEE
97views Hardware» more  VTS 2005»
14 years 20 days ago
Static Compaction of Delay Tests Considering Power Supply Noise
Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise est...
Jing Wang 0006, Xiang Lu, Wangqi Qiu, Ziding Yue, ...
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
14 years 1 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
DATE
2000
IEEE
114views Hardware» more  DATE 2000»
13 years 11 months ago
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...
Michael Münch, Norbert Wehn, Bernd Wurth, Ren...
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
13 years 11 months ago
Cycle-accurate macro-models for RT-level power analysis
 In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding