IP blocks and large macro cells are increasingly prevalent in physical design, actually causing an increase in the available free space for the dust logic. We observe that top-dow...
Many current integrated circuits designs, such as those released for the ISPD2005[14] placement contest, are extremely large and can contain a great deal of white space. These new...
We present a novel incremental placement methodology called FlowPlace for significantly reducing critical path delays of placed standard-cell circuits. FlowPlace includes: a) a t...
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the stateof-the-art after two decades of research in recursive ...
Andrew E. Caldwell, Andrew B. Kahng, Igor L. Marko...
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...