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DATE
2009
IEEE
145views Hardware» more  DATE 2009»
14 years 2 months ago
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal re...
Kai-Chiang Wu, Diana Marculescu
ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
13 years 9 months ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh
GLVLSI
2008
IEEE
204views VLSI» more  GLVLSI 2008»
14 years 2 months ago
NBTI resilient circuits using adaptive body biasing
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
Zhenyu Qi, Mircea R. Stan
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 2 months ago
Analysis and optimization of NBTI induced clock skew in gated clock trees
NBTI (Negative Bias Temperature Instability) has emerged as the dominant PMOS device failure mechanism for sub100nm VLSI designs. There is little research to quantify its impact o...
Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
14 years 19 days ago
Reliability- and process variation-aware placement for FPGAs
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
Assem A. M. Bsoul, Naraig Manjikian, Li Shang