High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...
Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer...
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
This paper studies microprocessor floorplanning considering thermal and throughput optimization. We first develop a stochastic heat diffusion model taking into account the appl...
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that ...
Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Yo...