30 search results - page 4 / 6 » An effective power mode transition technique in MTCMOS circu... |
DAC
1999
ACM
14 years 8 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
VLSID
2010
IEEE
13 years 1 months ago
2010
IEEE
The continuous increase of leakage power consumption
in deep sub-micro technologies necessitates more aggressive
leakage control. Runtime leakage control (RTLC) is effective,
si...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage curr...
ASPDAC
2000
ACM
13 years 12 months ago
2000
ACM
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...