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ITC
1998
IEEE
120views Hardware» more  ITC 1998»
14 years 24 days ago
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
13 years 6 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
DAC
2005
ACM
13 years 10 months ago
Efficient and accurate gate sizing with piecewise convex delay models
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
Hiran Tennakoon, Carl Sechen
ICDAR
2003
IEEE
14 years 1 months ago
Lexical Post-Processing Optimization for Handwritten Word Recognition
This paper presents a lexical post-processing optimization for handwritten word recognition. The aim of this work is to explore the combination of different lexical postprocessing...
Sabine Carbonnel, Éric Anquetil
DAC
2008
ACM
14 years 9 months ago
DeFer: deferred decision making enabled fixed-outline floorplanner
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
Jackey Z. Yan, Chris Chu