69 search results - page 4 / 14 » An event-guided approach to reducing voltage noise in proces... |
VLSID
2000
IEEE
14 years 8 days ago
2000
IEEE
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
CGO
2005
IEEE
14 years 1 months ago
2005
IEEE
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...
EUC
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...
ISLPED
1999
ACM
14 years 6 days ago
1999
ACM
As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. Howe...