139 search results - page 11 / 28 » An evolutionary algorithm for reducing integrated-circuit te... |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
— During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including builti...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in co...
VLSID
1998
IEEE
13 years 11 months ago
1998
IEEE
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
DDECS
2009
IEEE
13 years 11 months ago
2009
IEEE
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
DATE
2009
IEEE
2009
IEEE
Analyzing the impact of process variations on parametric measurements: Novel models and applications
14 years 2 months ago
Abstract—In this paper we propose a novel statistical framework to model the impact of process variations on semiconductor circuits through the use of process sensitive test stru...