257 search results - page 3 / 52 » An optimal algorithm for area minimization of slicing floorp... |
ASPDAC
1999
ACM
14 years 5 days ago
1999
ACM
In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new...
DATE
2010
IEEE
14 years 29 days ago
2010
IEEE
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
DAC
1992
ACM
13 years 12 months ago
1992
ACM
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...
ICCAD
1999
IEEE
14 years 5 days ago
1999
IEEE
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer inserti...