Sciweavers

117 search results - page 19 / 24
» An optimal algorithm for sizing sequential circuits for indu...
Sort
View
TCAD
2010
88views more  TCAD 2010»
13 years 2 months ago
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
DAC
2003
ACM
14 years 8 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
GECCO
2008
Springer
158views Optimization» more  GECCO 2008»
13 years 8 months ago
Structure and parameter estimation for cell systems biology models
In this work we present a new methodology for structure and parameter estimation in cell systems biology modelling. Our modelling framework is based on P systems, an unconl comput...
Francisco José Romero-Campero, Hongqing Cao...
DAC
2004
ACM
13 years 11 months ago
A methodology to improve timing yield in the presence of process variations
The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing...
Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wa...
DAC
2005
ACM
13 years 9 months ago
Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation
On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem ext...
Peng Li