117 search results - page 4 / 24 » An optimal algorithm for sizing sequential circuits for indu... |
DAC
2010
ACM
13 years 11 months ago
2010
ACM
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...
TCAD
2008
13 years 7 months ago
2008
Abstract-- In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT) algorithm called FLUTE. FLUTE is based on pre-computed lookup table to make RS...