208 search results - page 5 / 42 » Analog circuit simulation using range arithmetics |
DAC
1999
ACM
13 years 12 months ago
1999
ACM
This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used...
ISQED
2008
IEEE
14 years 1 months ago
2008
IEEE
The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or vo...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a novel concurrent fault simulator (called CONCERT) for nonlinear analog circuits. Three primary techniques in CONCERT, including fault ordering, state predict...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
DAC
2000
ACM
13 years 12 months ago
2000
ACM
Abstract: This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circ...