118 search results - page 1 / 24 » Analysis and Minimization of Test Time in a Combined BIST an... |
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
In this paper, an analysis of test time by CBET (which is an acronym for Combination of BIST and External Test) test approach is presented. The analysis validates that CBET test a...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architectu...
DFT
2003
IEEE
13 years 12 months ago
2003
IEEE
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
DSD
2005
IEEE
14 years 6 days ago
2005
IEEE
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...