118 search results - page 2 / 24 » Analysis and Minimization of Test Time in a Combined BIST an... |
DFT
2003
IEEE
13 years 12 months ago
2003
IEEE
A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-c...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
| This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some ac...
ISQED
2002
IEEE
13 years 11 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
ITC
2003
IEEE
13 years 12 months ago
2003
IEEE
1 This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a progr...
ATS
2004
IEEE
13 years 10 months ago
2004
IEEE
1 This paper describes a heuristic for system-on-chip test scheduling in an abort-on-fail context, where the test is terminated as soon as a defect is detected. We consider an hybr...