115 search results - page 12 / 23 » Analysis and optimization of gate leakage current of power g... |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
ARCS
2006
Springer
13 years 11 months ago
2006
Springer
State-of-the-art technologies in very large scale integration (VLSI) allow for the realization of gates with varying energy consumptions and hence delays (i.e., processing speeds) ...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
DAC
2004
ACM
14 years 1 months ago
2004
ACM
Leakage current has become a stringent constraint in today’s processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inver...