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» Analysis of communication delay bounds for network on chips
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CDC
2010
IEEE
151views Control Systems» more  CDC 2010»
13 years 4 months ago
Input output analysis of power control in wireless networks
In a wireless communication network different users share a common resource. An objective of radio resource management is to assign the resources in an effective way between the us...
Anders Moller, Ulf T. Jönsson
ETFA
2008
IEEE
13 years 10 months ago
Hardware acceleration for verifiable, adaptive real-time communication
Distributed real-time applications implement distributed applications with timeliness requirements. Such systems require a deterministic communication medium with bounded communic...
Sebastian Fischmeister, Insup Lee, Robert Trausmut...
INFOCOM
2003
IEEE
14 years 2 months ago
Statistical Per-Flow Service Bounds in a Network with Aggregate Provisioning
Abstract— Scalability concerns of QoS implementations have stipulated service architectures where QoS is not provisioned separately to each flow, but instead to aggregates of ï¬...
Jörg Liebeherr, Stephen D. Patek, Almut Burch...
SBCCI
2003
ACM
213views VLSI» more  SBCCI 2003»
14 years 2 months ago
Algorithms and Tools for Network on Chip Based System Design
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
Tang Lei, Shashi Kumar
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
14 years 5 months ago
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...