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» Analysis of power consumption in memory hierarchies
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TVLSI
2010
13 years 2 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 1 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
TVLSI
2008
139views more  TVLSI 2008»
13 years 7 months ago
Ternary CAM Power and Delay Model: Extensions and Uses
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Banit Agrawal, Timothy Sherwood
ISLPED
2005
ACM
88views Hardware» more  ISLPED 2005»
14 years 1 months ago
PARE: a power-aware hardware data prefetching engine
Aggressive hardware prefetching often significantly increases energy consumption in the memory system. Experiments show that a major fraction of prefetching related energy degrad...
Yao Guo, Mahmoud Ben Naser, Csaba Andras Moritz
ISVLSI
2006
IEEE
114views VLSI» more  ISVLSI 2006»
14 years 1 months ago
A Low Power Lookup Technique for Multi-Hashing Network Applications
Many network security applications require large virus signature sets to be maintained, retrieved, and compared against the network streams. Software applications frequently fail ...
Ilhan Kaya, Taskin Koçak