45 search results - page 5 / 9 » Analysis of power consumption on switch fabrics in network r... |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Current trends in high-performance parallel computers show that fat-tree interconnection networks are one of the most popular topologies. The particular characteristics of this to...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
DSD
2006
IEEE
14 years 1 months ago
2006
IEEE
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...