41 search results - page 5 / 9 » Analytical energy dissipation models for low-power caches |
NOCS
2009
IEEE
14 years 2 months ago
2009
IEEE
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
ISSS
2002
IEEE
14 years 9 days ago
2002
IEEE
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Recent breakthroughs in circuit and process technology have enabled new usage models for non-volatile memory technologies such as Flash and phase change RAM (PCRAM) in t...
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of...