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ICS
2007
Tsinghua U.
14 years 5 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
DAC
2006
ACM
14 years 4 months ago
Hierarchical power distribution and power management scheme for a single chip mobile processor
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method ...
Toshihiro Hattori, Takahiro Irita, Masayuki Ito, E...
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
14 years 4 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
DAC
2003
ACM
14 years 4 months ago
Crosstalk noise in FPGAs
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...
Yajun Ran, Malgorzata Marek-Sadowska
PLDI
1995
ACM
14 years 2 months ago
Corpus-Based Static Branch Prediction
Correctly predicting the direction that branches will take is increasingly important in today’s wide-issue computer architectures. The name program-based branch prediction is gi...
Brad Calder, Dirk Grunwald, Donald C. Lindsay, Jam...