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» Application of Reduce Order Modeling to Time Parallelization
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ASPLOS
2012
ACM
13 years 10 months ago
Providing safe, user space access to fast, solid state disks
Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state...
Adrian M. Caulfield, Todor I. Mollov, Louis Alex E...
CODES
2005
IEEE
15 years 8 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
KIVS
1999
Springer
15 years 6 months ago
Adaptive Scheduling of Multimedia Documents
Multimedia presentations are applicable in various domains such as advertising, commercial presentations or education. Multimedia presentations are described by multimedia documen...
Stefan Wirag
EVOW
2001
Springer
15 years 7 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
126
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TR
2010
159views Hardware» more  TR 2010»
14 years 9 months ago
Accelerated Degradation Tests Applied to Software Aging Experiments
Abstract--In the past ten years, the software aging phenomenon has been systematically researched, and recognized by both academic, and industry communities as an important obstacl...
Rivalino Matias, Pedro Alberto Barbetta, Kishor S....