In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an impor...
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis m...
In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature...
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri