As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires ...
N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheun...
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinab...
We develop a neural network that learns to separate the nominal from the faulty instances of a circuit in a measurement space. We demonstrate that the required separation boundari...
In this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier ...