Sciweavers

1398 search results - page 100 / 280
» Application-Specific Integrated Circuits
Sort
View
ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
14 years 2 months ago
Characterisation of FPGA Clock Variability
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires ...
N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheun...
ISQED
2007
IEEE
128views Hardware» more  ISQED 2007»
14 years 2 months ago
A Model for Timing Errors in Processors with Parameter Variation
Parameter variation in integrated circuits causes sections of a chip to be slower than others. To prevent any resulting timing errors, designers have traditionally designed for th...
Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
DATE
2005
IEEE
112views Hardware» more  DATE 2005»
14 years 1 months ago
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinab...
GLVLSI
2005
IEEE
133views VLSI» more  GLVLSI 2005»
14 years 1 months ago
Generating decision regions in analog measurement spaces
We develop a neural network that learns to separate the nominal from the faulty instances of a circuit in a measurement space. We demonstrate that the required separation boundari...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
SBCCI
2005
ACM
132views VLSI» more  SBCCI 2005»
14 years 1 months ago
Design and power optimization of CMOS RF blocks operating in the moderate inversion region
In this work the design of radiofrequency CMOS circuit blocks in the 910MHz ISM band, while biasing the MOS transistor in the moderate inversion region, is analyzed. An amplifier ...
Leonardo Barboni, Rafaella Fiorelli