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TCAD
2008
93views more  TCAD 2008»
13 years 8 months ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
TVLSI
2008
99views more  TVLSI 2008»
13 years 7 months ago
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
Sheng-Chih Lin, Kaustav Banerjee
VLSID
2010
IEEE
190views VLSI» more  VLSID 2010»
13 years 6 months ago
Rethinking Threshold Voltage Assignment in 3D Multicore Designs
Due to the inherent nature of heat flow in 3D integrated circuits, stacked dies exhibit a wide range of thermal characteristics. The strong dependence of leakage with temperature...
Koushik Chakraborty, Sanghamitra Roy
ICCAD
2009
IEEE
106views Hardware» more  ICCAD 2009»
13 years 5 months ago
Quantifying robustness metrics in parameterized static timing analysis
Process and environmental variations continue to present significant challenges to designers of high-performance integrated circuits. In the past few years, while much research has...
Khaled R. Heloue, Chandramouli V. Kashyap, Farid N...
ATS
2010
IEEE
250views Hardware» more  ATS 2010»
13 years 4 months ago
Efficient Embedding of Deterministic Test Data
Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor techn...
Mudassar Majeed, Daniel Ahlstrom, Urban Ingelsson,...