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DATE
2002
IEEE
73views Hardware» more  DATE 2002»
14 years 28 days ago
A Burst-Mode Oriented Back-End for the Balsa Synthesis System
This paper introduces several new component clustering techniques for the optimization of asynchronous systems. In particular, novel “Burst-Mode aware” restrictions are impose...
Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley...
GLVLSI
2010
IEEE
131views VLSI» more  GLVLSI 2010»
14 years 24 days ago
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...
Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, T...
DAC
2009
ACM
14 years 19 days ago
Serial reconfigurable mismatch-tolerant clock distribution
We present an unconventional clock distribution that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modu...
Atanu Chattopadhyay, Zeljko Zilic
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
14 years 13 days ago
Detailed routing architectures for embedded programmable logic IP cores
As the complexity of integrated circuits increases, the ability to make post-fabrication changes to fixed ASIC chips will become more and more attractive. This ability can be real...
Peter Hallschmid, Steven J. E. Wilton
DATE
2000
IEEE
82views Hardware» more  DATE 2000»
14 years 11 days ago
Constructive Library-Aware Synthesis Using Symmetries
In this paper a constructive library-aware multilevel logic synthesis approach using symmetries is described. It integrates the technology-independent and technologydependent stag...
Victor N. Kravets, Karem A. Sakallah