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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
14 years 19 days ago
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints
In this paper, a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and a...
Robert Schwencker, Josef Eckmueller, Helmut E. Gra...
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
14 years 3 months ago
Test architecture design and optimization for three-dimensional SoCs
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
Li Jiang, Lin Huang, Qiang Xu
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
14 years 24 days ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
DAC
2007
ACM
14 years 7 days ago
CAD Implications of New Interconnect Technologies
This paper looks at the CAD implications of possible new interconnect technologies. We consider three technologies in particular: three dimensional ICs, carbon nanotubes as a repl...
Louis Scheffer
DAC
2006
ACM
14 years 2 months ago
Tomorrow's analog: just dead or just different?
This panel discusses the following topics. With the ongoing trend towards more and more digitization in applications ranging from multimedia to telecommunications, there is a big ...
Shekhar Y. Borkar, Robert W. Brodersen, Jue-Hsien ...