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SLIP
2009
ACM
14 years 2 months ago
Floorplan-based FPGA interconnect power estimation in DSP circuits
A novel high-level approach for estimating power consumption of global interconnects in data-path oriented designs implemented in FPGAs is presented. The methodology is applied to...
Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic
AHS
2006
IEEE
164views Hardware» more  AHS 2006»
14 years 2 months ago
Automatic Hybrid Genetic Algorithm Based Printed Circuit Board Inspection
The paper presents a novel integrated system in which a number of image processing algorithm are embedded within a Genetic Algorithm (GA) based framework in order to provide an ad...
Syamsiah Mashohor, Jonathan R. Evans, Ahmet T. Erd...
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
14 years 2 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
SBCCI
2006
ACM
126views VLSI» more  SBCCI 2006»
14 years 2 months ago
Power constrained design optimization of analog circuits based on physical gm/ID characteristics
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
Alessandro Girardi, Sergio Bampi
DATE
2005
IEEE
148views Hardware» more  DATE 2005»
14 years 1 months ago
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits
Multi-channel waveform monitoring technique enhances built-in test and diagnostic capability of mixed-signal VLSI circuits. An 8-channel prototype system incorporates adaptive sam...
Koichiro Noguchi, Makoto Nagata