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» Applying Logic Synthesis for Speeding Up SAT
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DAC
2003
ACM
14 years 9 months ago
Temporofunctional crosstalk noise analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H...
CAV
2008
Springer
139views Hardware» more  CAV 2008»
13 years 10 months ago
CSIsat: Interpolation for LA+EUF
We present CSIsat, an interpolating decision procedure for the quantifier-free theory of rational linear arithmetic and equality with uninterpreted function symbols. Our implementa...
Dirk Beyer, Damien Zufferey, Rupak Majumdar
VLSID
2006
IEEE
156views VLSI» more  VLSID 2006»
14 years 8 months ago
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrish...
IEEEHPCS
2010
13 years 5 months ago
Fast learning for multibiometrics systems using genetic algorithms
The performance (in term of error rate) of biometric systems can be improved by combining them. Multiple fusion techniques can be applied from classical logical operations to more...
Romain Giot, Mohamad El-Abed, Christophe Rosenberg...
DAC
2005
ACM
14 years 9 months ago
FPGA technology mapping: a study of optimality
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...