Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
Linear programming (LP) in its many forms has proven to be an indispensable tool for expressing and solving optimization problems in numerous domains. We propose the first set of ...