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    ISCA
    2008
    IEEE
    201views Hardware» more  ISCA 2008»
    iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
    13 years 7 months ago
    iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
    Download  oucsace.cs.ohiou.edu
    Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
    Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
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    APWEB
    2008
    Springer
    124views Internet Technology» more  APWEB 2008»
    An Energy-Efficient Multi-agent Based Architecture in Wireless Sensor Network
    13 years 9 months ago
    An Energy-Efficient Multi-agent Based Architecture in Wireless Sensor Network
    Download  ilab1.korea.ac.kr
    Wireless sensor network (WSN) containing thousands of tiny and low-power nodes can be used to monitor environment. An energy-efficient and reliable wireless communication architect...
    Yi-Ying Zhang, WenCheng Yang, Kee-Bum Kim, Min-Yu ...
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    DATE
    2006
    IEEE
    134views Hardware» more  DATE 2006»
    Energy efficiency vs. programmability trade-off: architectures and design principles
    14 years 1 months ago
    Energy efficiency vs. programmability trade-off: architectures and design principles
    Download  www.date-conference.com
    Pablo Robelly, Hendrik Seidel, K. C. Chen, Gerhard...
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    DATE
    2005
    IEEE
    84views Hardware» more  DATE 2005»
    Tag Overflow Buffering: An Energy-Efficient Cache Architecture
    14 years 29 days ago
    Tag Overflow Buffering: An Energy-Efficient Cache Architecture
    Download  www.date-conference.com
    Mirko Loghi, Paolo Azzoni, Massimo Poncino
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    ASPDAC
    2004
    ACM
    94views Hardware» more  ASPDAC 2004»
    Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)
    14 years 24 days ago
    Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)
    Download  www.ics.uci.edu
    Aviral Shrivastava, Nikil D. Dutt
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