110 search results - page 9 / 22 » Architectural simulation for a programmable DSP chip set |
WETICE
2007
IEEE
14 years 1 months ago
2007
IEEE
Designing a collaborative architecture for real-time applications is an intricate challenge that usually involves dealing with the real-time constraints, resource limitations and ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memorie...
VLSID
2004
IEEE
14 years 7 months ago
2004
IEEE
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
TC
2008
13 years 7 months ago
2008
Security is gaining relevance in the development of embedded devices. Toward a secure system at each level of design, this paper addresses security aspects related to Network-on-Ch...
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...