Sciweavers

56 search results - page 7 / 12
» Architectural support for low overhead detection of memory v...
Sort
View
HPCA
2008
IEEE
14 years 8 months ago
Thread-safe dynamic binary translation using transactional memory
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application...
JaeWoong Chung, Michael Dalton, Hari Kannan, Chris...
MICRO
2008
IEEE
103views Hardware» more  MICRO 2008»
14 years 2 months ago
Testudo: Heavyweight security analysis via statistical sampling
Heavyweight security analysis systems, such as taint analysis and dynamic type checking, are powerful technologies used to detect security vulnerabilities and software bugs. Tradi...
Joseph L. Greathouse, Ilya Wagner, David A. Ramos,...
DATE
2004
IEEE
133views Hardware» more  DATE 2004»
13 years 11 months ago
Channel Decoder Architecture for 3G Mobile Wireless Terminals
Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In thirdgeneration...
Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
14 years 2 months ago
ECMon: exposing cache events for monitoring
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
Vijay Nagarajan, Rajiv Gupta
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 8 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das