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144
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IEEEPACT
2003
IEEE
15 years 9 months ago
Memory Hierarchy Design for a Multiprocessor Look-up Engine
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal...
129
Voted
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
15 years 5 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
108
Voted
FCCM
2008
IEEE
118views VLSI» more  FCCM 2008»
15 years 10 months ago
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
François Charot, Christophe Wolinski, Nicol...
113
Voted
IPPS
2005
IEEE
15 years 9 months ago
TiNy Threads: A Thread Virtual Machine for the Cyclops64 Cellular Architecture
This paper presents the design and implementation of a thread virtual machine, called TNT (or TiNy-Threads) for the IBM Cyclops64 architecture (the latest Cyclops architecture tha...
Juan del Cuvillo, Weirong Zhu, Ziang Hu, Guang R. ...
98
Voted
ISCAS
2003
IEEE
112views Hardware» more  ISCAS 2003»
15 years 9 months ago
Architectures for function evaluation on FPGAs
This paper presents a new family of architectures for multi-cycle area-efficient evaluation of elementary and composite functions, and an exploration of the design tradeoffs for i...
Nalin Sidahao, George A. Constantinides, Peter Y. ...